Static Power Dissipation Reduction on Full Subtractor Using Mtcmos
نویسنده
چکیده
Power dissipation has become one of the major concerns of VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, a Full Subtarctor is designed using different leakage power reduction techniques like MTCMOS, Variable Body-Bias Technique. All the above mentioned techniques are simulated using Tanner tool in TSMC018 technology.
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